1. Field of the Invention
This invention generally relates to semiconductor processing and, more particularly, to a method of etching silicon nitride disposed over silicon oxide to form nitride spacers.
2. Description of Related Art
During the manufacture of miniaturized devices, intermediate and/or final structures are often formed with combinations of patterned materials composed of oxides and nitrides of silicon disposed adjacent to one another. The oxides and nitrides may be further disposed adjacent to monocrystalline, polycrystalline, or other forms of silicon. It is often times desirable to strip away or otherwise etch the silicon nitride (“nitride”) material while not significantly etching into adjacent silicon or silicon oxide (“oxide”).
For example, transistors are generally manufactured by placing an undoped polycrystalline silicon (“polysilicon”) material over a semiconductor substrate. The polysilicon material is generally separated from the semiconductor substrate by an insulating layer, usually a relatively thin layer of oxide, such as silicon dioxide. The polysilicon material and the oxide are then patterned to form a gate arranged upon a gate oxide with source/drain regions adjacent to and on opposite sides of the gate. The gate and source/drain regions are then implanted with a dopant species. A channel region forms between the source/drain regions. The insulating layer is provided to prevent current from flowing between the gate and the source/drain regions or the channel region.
When scaling to smaller device geometries or operating transistors which have heavily doped source/drain regions arranged directly adjacent to the gate, a problem known as the hot carrier effect is encountered. Large potential gradients and/or shorter channel lengths, with resultant higher electric fields, cause the kinetic energy of the charged carriers to increase and thereby produce “hot” or energetic electrons. These electrons can become injected into and trapped within the gate oxide. Because of carrier entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate over time, ultimately leading to device performance degradation or even, in some instances, device failure. The hot carrier effect is therefore a function of gate oxide thickness and overlap between the gate and the source/drain regions.
To overcome problems resulting from the hot carrier effect, alternative source/drain structures may be used. Alternative source/drain structures are often times formed by depositing and etching silicon nitride to create nitride spacers adjacent to the gate. The spacers will mask and align dopant and implant regions within the semiconductor substrate. Nitride is often chosen because it is a fairly stable material and is nearly impervious to diffusion, making it an excellent barrier material. Because of the effect that the length of doped regions has on circuit attributes (e.g., drive current), it is important that the thickness of these doped regions be as close to the desired values as possible. Consequently, it is desirable that there be a high degree of thickness uniformity in the formation of the spacers, which directly affect the formation of the doped regions. Accordingly, the thickness of etched spacers should vary as little as possible from desired values, with vertical profiles being preferred over sloped profiles. Spacer thickness uniformity should occur both across each spacer and from spacer to spacer.
A high degree of etch anisotropy is also desirable to produce vertical sidewalls for the nitride spacers, thereby conforming to the required critical dimension for submicron geometries from the top to the bottom of the nitride spacer. A low degree of etch anisotropy will produce undesirable sloping sidewalls, causing deviations from the required critical dimension.
Further, nitride spacers are often times formed from a nitride layer disposed over a liner oxide layer which is disposed over the gate and used as an etch stop and insulator. Because nitride etching often takes place in the presence of oxide, the etching must be selective so as to not overly remove any exposed oxide or oxide underneath the nitride layer, possibly resulting in oxide “punchthrough,” while also not leaving any nitride residue between adjacent spacer structures, possibly resulting in nitride “stringers” that can cause device degradation. Selectivity is defined by the ratio of component etch rates. Thus, nitride to oxide selectivity is defined by:       Selectivity          Nitride      /      Oxide        =            Etch      ⁢                           ⁢      rate      ⁢                           ⁢      of      ⁢                           ⁢      Nitride      ⁢                           ⁢              (                  Å          /          min                )                    Etch      ⁢                           ⁢      rate      ⁢                           ⁢      of      ⁢                           ⁢      Oxide      ⁢                           ⁢              (                  Å          /          min                )            Accordingly, a high selectivity for etching of nitride over oxide is important for accurately controlling the etch end point and for preventing damage to the gate or silicon substrate from overetching of the liner oxide layer, which itself is becoming increasingly thin with decreasing device features.
Therefore, with circuit densities increasing, a need exists for an improved method to form nitride spacers over a thin oxide layer with good uniformity, profile, and selectivity characteristics.